1. Field of the Invention
The present invention generally relates to a multiple processor type computing system and, more particularly, to a multiple processor type computing system which uses modified LAN connection circuitry to interconnect multiple processors within a common computer housing.
2. Description of Related Art
It has long been appreciated that significant advantages, particularly in the area of processing capability, are derived by interconnecting one or more processor subsystems. In the past, however, processor interconnectivity has primarily been contemplated in connection with multiprocessing or parallel processing environments. Multiprocessing is the simultaneous processing of two or more portions of the same program by two or more processor subsystems. Parallel processing, on the other hand, is the use of concurrency in the operation of a computer system to increase throughput, increase fault tolerance, or reduce the time needed to solve particular problems. Typically, concurrency is increased by the use of either pipelining, whereby an operation is divided into multiple stages to be performed by separate processor subsystems, or parallelism, whereby, like multiprocessing, multiple processor subsystems are used to perform a single task.
Recently, considerable attention has been focussed on interconnecting various independent computer systems into a network. One such interconnection of plural computer systems is achieved by use of a local area network (or "LAN"). For example, a LAN may be used to support a range of professional, scientific, engineering, and/or administrative workstations requiring communal access to shared information storage and processing facilities and/or the interchange of documents.
While geographically constrained, the LAN has numerous advantages, including its provision for direct interconnection between the various computer systems or other devices placed in the LAN. Accordingly, the LAN avoids many routing problems which characterize other types of networks. Furthermore, since there are no switching elements or buffers in the network, the only network resource for which computer systems placed in the network have to contend is the transmission medium itself. Of course, such a computer system will also have to contend for the attention of the other computer systems or other devices with which it wishes to communicate. However, all such contention and associated buffering takes place in the computer systems and/or the devices themselves and not the network.
Various techniques may be used to attach a computer system to a LAN. One technique would be to interconnect the computer system to the LAN through the computer's serial port. Such a LAN is commonly referred to as an RS-232 or zero slot LAN. While relatively inexpensive, RS-232 LANs are characterized by relatively slow data rates, typically on the order of 150 kb/s per second, and are suitable only for small offices that have only a few workstations. Another technique utilizes a specially designed adapter card which is inserted in an available slot on the expansion bus of the computer system. While the additional circuitry adds to the cost of installing the LAN, the increased data rates, typically on the order of 10 mb/s per second, make such LANs preferable over RS-232 LANs.
The ever increasing numbers and types of computer systems have led to various attempts to use computer systems interconnected by a LAN in a multiple processor environment commonly referred to as "enterprise" computing. While one factor motivating the development of enterprise computing has been the increased processing capability achievable by utilizing multiple processors to perform a task, another factor has been the desire to provide a computer capable of using software operable with different processor subsystems and/or operating systems. It should be readily appreciated that the ability to run software written for different operating systems, for example, the NT, OS2, UNIX and Windows systems, from a single workstation specially designed to be able to access an appropriate processor, for example, the Intel Pentium, DEC Alpha, Motorola Power PC and HP RISC, interconnected therewith would have a tremendous commercial advantage over a traditionally designed workstation.
Referring now to FIG. 1, a conventional, LAN-type interconnection between first and second computer systems will now be described in greater detail. A first computer system 10, typically housed within a first computer chassis 11 and physically located at a first location, is comprised of a local bus 15 configured for bi-directional exchanges of address, data and control signals between various components of the computer system 10 such as central processing unit (or "CPU") 14 and main memory 16. It should be clearly understood, however, that additional devices, for example, a memory controller for controlling exchanges between the CPU 14 and the main memory 16 and a cache that contains data and instructions obtained from main storage for next use by the CPU 14, typically reside on the local bus 15 of computer system such as the computer system 10 but have been omitted from FIG. 1 for ease of illustration.
Also residing on the local bus 15 is a peripheral connection interface (or "PCI") controller 18 which controls exchanges of address, data and control signals between devices residing on the local bus 15, for example, the CPU 14, and devices residing on a PCI bus 20 coupled to the local bus 15 by a bridge 22. Preferably, the PCI bus 20 should be a 32-bit wide bus having a transfer rate on the order of 33 MBytes per second. Residing on the PCI bus 20 are a main basic input output system (or "BIOS") 24 and plural peripheral devices. The main BIOS 24 is that portion of the disk operating system (or "DOS") which provides an interface between the DOS kernel and the underlying hardware. More specifically, the DOS kernel passes commands from application software to the main BIOS 24 for translation into hardware-specific requests. During start-up of the computer system 10, the main BIOS 24 is also responsible for initializing input/output (or "I/O") devices installed on the PCI bus 20. In some cases, however, an expansion BIOS (not shown) which resides on a particular I/O device installed on the PCI bus 20 is also required to initialize that particular device.
Also residing on the PCI bus 20 are plural peripheral devices such as an auxiliary memory 26, an addressable storage space, for example, a small computer system interface (or "SCSI") drive, which typically contains large amounts of data infrequently required by the CPU 14 and a display system 28, for example, a video monitor, which visually displays data. Finally, the PCI bus 20 includes a PCI interface 32 which, as will be more fully described below, is used to interconnect a first LAN device 58 to the PCI bus 20. It should be clearly understood, however, that the particular devices identified as residing on the PCI bus 20 are exemplary and that numerous other I/O and/or peripheral devices not specifically enumerated herein, for example, a printer, may also reside on the PCI bus 20.
A bridge 29 couples the PCI bus 20 with an industry standard architecture (or "ISA") bus 30. The ISA bus 30 is a 16-bit wide bus having plural expansion slots (not shown) in which additional devices, generally referred to as option cards (also not shown), may be inserted to augment the capabilities of the computer system 10.
Also illustrated in FIG. 1 is a second computer system 12 which, when coupled to the first computer system 10 in a manner to be more fully described below, may exchange address, data and control signals therewith. As illustrated herein, the second computer system 12 is housed within a second computer chassis 13, physically located at a second location and configured identically to the first computer system 10, i.e. the second computer system 12 is comprised of a local bus 40 on which a CPU 34, main memory 36 and PCI controller 38 reside, a PCI bus 42 on which a main BIOS 44, an auxiliary memory 46, a display system 48 and a PCI interface 50 used to interconnect a second LAN device 60 to the PCI bus 42 reside, an ISA bus 52, a bridge 54 which couples the local bus 40 and the PCI bus 42 and a bridge 56 which couples the PCI bus 42 and the ISA bus 52. It should be clearly understood, however, that the first and second computer systems 10 and 12 have been identically configured merely for ease of description and that it is specifically contemplated that the first and second computer systems 10 and 12 may be variously configured computer systems which differ as to either the particular components and/or devices installed on the local, PCI and ISA busses 40, 42 and 52 and/or as to the particular type of processor selected as the CPU 34.
Continuing to refer to FIG. 1, the interconnection between the first computer system 10 and the second computer system 12 which permits the exchange of address, data and control signals therebetween will now be described in greater detail. To interconnect the two, the first LAN device 58 is coupled to the PCI bus 20 of the first computer system 10 by inserting the first LAN device 58 into the PCI interface 32. The first LAN device 58 is comprised of data registers 62, first-in-first out (or "FIFO") data registers 64, a LAN controller 66 and a serial I/O port 68, all of which are interconnected with each other by internal interconnection circuitry 59, for example, a series of conductive leads. Similarly, a second LAN device 60 is coupled to the PCI bus 42 of the second computer system 12 by inserting the second LAN device 60 into the PCI interface 50. As illustrated herein, the first and second LAN devices 58 and 60 are identically configured, i.e., the second LAN device 60 is comprised of data registers 70, FIFO data registers 72, a LAN controller 74 and a serial I/O port 76 interconnected with each other by internal interconnection circuitry 61. It is specifically contemplated, however, that the first and second LAN devices 58 and 60 may be variously configured in a manner not illustrated herein. Finally, physical interconnection between the first computer system 10 and the second computer system 12 is achieved using a physical link 78 which connects the first serial I/O port 68 and the second serial I/O port 76. For example, the physical link 78 may be coaxial cable or twisted-pair wires.
The precise protocol by which address, data and control signals are exchanged between the first computer system 10 and the second computer system 12 using the first and second LAN devices 58 and 60 will vary depending on the particular LAN devices installed in the respective computer systems. For example, in accordance with one such protocol, if the CPU 14 of the first computer system 10 desired to issue an instruction to the CPU 34 of the second computer system 12, the PCI controller 18 would arrange for the transfer of the command to the data registers 62. The PCI controller 18 would then inform the LAN controller 66 of the transfer. 0f course, if the information to be transferred from the first computer system 10 to the second computer system 12 required buffering, for example, due to the size of the information being transferred and the rate at which such information could be accepted at its ultimate destination, such information would be placed in the data FIFO 64 instead. In turn, the LAN controller 66 would then arrange for the transfer of the contents of the data registers 62 or data FIFO 64 to the CPU 34, for example, by arranging an interrupt of the CPU 34 followed by a transfer of the contents of the data registers 62 to the CPU 34 via the serial I/O port 68, the physical link 78, the serial I/O port 76, the PCI bus 42 and the local bus 40. 0f course, the transfer of address, data and control signals from the second computer system 12 to the first computer system 10 would be achieved in the reverse manner, i.e. by transferring the information into either the data registers 70 or the data FIFO 72, notifying the LAN controller 74 of the transfer and having the LAN controller 74 arrange for the transfer of the information to its final destination via the serial I/O port 76, the physical link 78, the serial I/O port 68 and the PCI bus 20.
It will be readily appreciated by one skilled in the art that, while the interconnection of the first and second computer systems 10 and 12 using the physical link 78 and the first and second LAN devices 58 and 60 illustrated in FIG. 1 may permit the CPU 14 to utilize the CPU 34 to perform multiple processor tasks including the execution of software written for a different processor type, numerous shortcomings in the illustrated interconnection of the first and second computer systems 10 and 12 limit its usefulness as a multiple processor computer system. In particular, the serial interconnection between the first and second computer systems 10 and 12 severely limit the rate at which information may be transferred between the systems. Furthermore, plural redundant devices make the multiple processor system achieved by the interconnection of the first and second computer systems 10 and 12 unnecessarily expensive.
It can be readily seen from the foregoing that it would be desirable to provide a simple and inexpensive multiple processor computing system capable of executing software designed for use in various platforms and/or operating systems. It is, therefore, the object of this invention to provide such a multiple processor type computing system.